MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-FlopFebruary 1990Revised May 1999
MM74HCT573 • MM74HCT574
Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop
General Description
The MM74HCT573 octal D-type latches andMM74HCT574 octal D-type flip-flop advanced silicon-gateCMOS technology, which provides the inherent benefits oflow power consumption and wide power supply range, butare LS-TTL input and output characteristic and pin-outcompatible. The 3-STATE outputs are capable of driving 15LS-TTL loads. All inputs are protected from damage due tostatic discharge by internal diodes to VCC and ground.When the MM74HCT573 Latch Enable input is HIGH, theQ outputs will follow the D inputs. When the Latch Enablegoes LOW, data at the D inputs will be retained at the out-puts until Latch Enable returns HIGH again. When a highlogic level is applied to the Output Control input, all outputsgo to a high impedance state, regardless of what signalsare present at the other inputs and the state of the storageelements.
The MM74HCT574 are positive edge triggered flip-flops.Data at the D inputs, meeting the setup and hold timerequirements, are transferred to the Q outputs on positive
going transitions of the Clock (CK) input. When a high logiclevel is applied to the Output Control (OC) input, all outputsgo to a high impedance state, regardless of what signalsare present at the other inputs and the state of the storageelements.
The MM74HCT devices are intended to interface betweenTTL and NMOS components and standard CMOS devices.These parts are also plug in replacements for LS-TTLdevices and can be used to reduce power consumption inexisting designs.
Features
sTTL input characteristic compatiblesTypical propagation delay: 18 nssLow input current: 1 µA maximumsLow quiescent current: 80 µA maximum sCompatible with bus-oriented systemssOutput drive capability: 15 LS-TTL loads
Ordering Codes:
Order NumberMM74HCT573WMMM74HCT573SJMM74HCT573MTCMM74HCT573NMM74HCT574WMMM74HCT574SJMM74HCT574MTCMM74HCT574N
Package Number
M20BM20DMTC20N20AM20BM20DMTC20N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor CorporationDS010627.prfwww.fairchildsemi.com
元器件交易网www.cecb2b.com
MM74HCT573 • MM74HCT574Connection DiagramsTruth Tables
MM74HCT573
Output Control
LLLH
LEHHLX
DataHLXX
OutputHLQ0Z
H = HIGH LevelL = LOW Level
Q0 = Level of output before steady-state input conditions were established.Z = High Impedance State
Top ViewMM74HCT573
MM74HCT574
Output Control
LLLH
LE↑↑LX
DataHLXX
OutputHLQ0Z
H = HIGH LevelL = LOW Level
Q0 = Level of output before steady-state input conditions were established.X = Don’t Care
Z = High Impedance State
↑ = Transition from LOW-to-HIGH
Top ViewMM74HCT574
www.fairchildsemi.com2
元器件交易网www.cecb2b.com
MM74HCT573 • MM74HCT574 Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC)DC Input Voltage (VIN)DC Output Voltage (VOUT)Clamp Diode Current (IIK, IOK)DC Output Current, per pin (IOUT)DC VCC or GND Current, per pin (ICC)Storage Temperature Range (TSTG)Power Dissipation (PD)(Note 3)
S. O. Package onlyLead Temperature (TL) (Soldering 10 seconds)
260°C600 mW500 mW−0.5 to +7.0V−1.5 to VCC+ 1.5V−0.5 to VCC+ 0.5V
± 20 mA± 35 mA± 70 mA
−65°C to +150°C
Recommended OperatingConditions
Min
Supply Voltage (VCC)DC Input or Output Voltage(VIN, VOUT)
Operating Temperature Range (TA)Input Rise or Fall Timestr, tf
500
ns
Note 1: Absolute Maximum Ratings are those values beyond which dam-age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.Note 3: Power Dissipation temperature derating — plastic “N” package: −12 mW/°C from 65°C to 85°C.
Max5.5VCC+85
UnitsVV°C
4.50−40
DC Electrical Characteristics
VCC = 5V ± 10% (unless otherwise specified)SymbolVIHVILVOH
Parameter
Minimum HIGH LevelInput VoltageMaximum LOW LevelInput VoltageMinimum HIGH LevelOutput Voltage
VIN = VIH or VIL|IOUT| = 20 µA
|IOUT| = 6.0 mA, VCC = 4.5V|IOUT| = 7.2 mA, VCC = 5.5V
VOL
Maximum LOW LevelVoltage
VIN = VIH or VIL|IOUT| = 20 µA
|IOUT| = 6.0 mA, VCC = 4.5V|IOUT| = 7.2 mA, VCC = 5.5V
IINIOZ
Maximum InputCurrent
Maximum 3-STATEOutput LeakageCurrent
ICC
Maximum QuiescentSupply Current
VIN = VCC or GNDIOUT = 0 µA
VIN = 2.4V or 0.5V (Note 4)
Note 4: Measured per pin. All others tied to VCC or ground.
Conditions
TA = 25°CTyp
2.00.8
TA = −40 to 85°CTA = −55 to 125°C
Guaranteed Limits
2.00.8
2.00.8
UnitsVV
VCC4.25.700.20.2
VCC − 0.13.984.980.10.260.26±0.1
VCC − 0.13.844.840.10.330.33±1.0
VCC − 0.13.74.70.10.40.4±1.0
V
V
VIN = VCC or GND,VIH or VIL
VOUT = VCC or GNDEnable = VIH or VIL
µA
±0.5±5.0±10µA
8.01.5
801.8
1602.0
µAmA
3www.fairchildsemi.com
元器件交易网www.cecb2b.com
MM74HCT573 • MM74HCT574AC Electrical Characteristics MM74HCT573
VCC = 5.0V, tr = tf = 6 ns, TA = 25°C (unless otherwise specified)SymboltPHLtPLHtPHLtPLHtPZHtPZLtPHZtPLZtWtStH
Parameter
Maximum Propagation DelayData to Output
Maximum Propagation DelayLatch Enable to Output
Maximum Enable Propagation DelayControl to Output
Maximum Disable Propagation DelayControl to Output
Minimum Clock Pulse WidthMinimum Setup Time Data to ClockMinimum Hold Time Clock to Data
CL = 45 pFRL = 1 kΩCL = 5 pFRL = 1 kΩCL = 45 pFConditionsCL = 45 pF
Typ17162114
Guaranteed Limit
2727302315512
Unitsnsnsnsnsnsnsns
AC Electrical Characteristics MM74HCT573
VCC= 5.0V ± 10%, tr = tf = 6 ns (unless otherwise specified)SymboltPHLtPLHtPHLtPLHtPZHtPZLtPHZtPLZtTHLtTLHtWtStHCINCOUTCPD
Parameter
Maximum PropagationDelay Data to OutputMaximum Propagation DelayLatch Enable to OutputMaximum Enable PropagationDelay Control to OutputMaximum Disable PropagationDelay Control to OutputMaximum Output Rise and Fall Time
Minimum Clock Pulse WidthMinimum Setup Time Data to ClockMinimum Hold Time Clock to DataMaximum Input CapacitanceMaximum Output CapacitancePower Dissipation Capacitance (Note 5)
OC = VCCOC = GND
−34
CL = 50 pFRL = 1 kΩCL = 50 pFRL = 1 kΩCL = 50 pFCL = 50 pFConditionsCL = 50 pF
TA = 25°Typ181722156
3030303012155121020552
TA = −40 to 85°CTA = −55 to 125°CGuaranteed Limits
3844383815206151020
4553454518248181020
UnitsnsnsnsnsnsnsnsnspFpFpF
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f+ICC VCC, and the no load dynamic current consumption, IS = CPDVCCf+ICC.
www.fairchildsemi.com4
元器件交易网www.cecb2b.com
MM74HCT573 • MM74HCT574 AC Electrical Characteristics MM74HCT574
VCC = 5.0V, tr = tf = 6 ns, TA = 25°CSymbolfMAXtPHLtPLHtPZHtPZLtPHZtPLZtWtStH
Parameter
Maximum Clock FrequencyMaximum Propagation Delayto Output
Maximum Enable Propagation DelayControl to Output
Maximum Disable Propagation DelayControl to Output
Minimum Clock Pulse WidthMinimum Setup Time Data to ClockMinimum Hold Time Clock to Data
CL = 45 pFRL = 1 kΩCL = 45 pFRL = 1 kΩCL = 45 pFConditions
Typ60171914
Guaranteed Limit
3327282515125
UnitsMHznsnsnsnsnsns
AC Electrical Characteristics MM74HCT574
VCC = 5.0V ± 10%, tr = tf = 6 ns (unless otherwise specified)SymbolfMAXtPHLtPLHtPZHtPZLtPHZtPLZtTHLtTLHtWtStHCINCOUTCPD
Parameter
Maximum Clock FrequencyMaximum Propagation DelayClock to Output
Maximum Enable PropagationDelay Control to OutputMaximum Disable PropagationDelay Control to OutputMaximum OutputRise and Fall Time
Minimum Clock Pulse WidthMinimum Setup Time Data to ClockMinimum Hold Time Clock to DataMaximum Input CapacitanceMaximum Output CapacitancePower Dissipation Capacitance(Note 6)
OC = VCCOC = GND
5586−1
CL = 50 pFRL = 1 kΩCL = 50 pFRL = 1 kΩCL = 50 pFCL = 50 pF
1822156
Conditions
TA = 25°CTyp
3330303012151251020
TA = −40 to 85°CTA = −55 to 125°C
Guaranteed Limits2838383815201561020
2345454518241881020
UnitsMHznsnsnsnsnsnsnspFpFpF
Note 6: CPD determines the no load power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC.
5www.fairchildsemi.com
元器件交易网www.cecb2b.com
MM74HCT573 • MM74HCT574Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
www.fairchildsemi.com
6
元器件交易网www.cecb2b.com
MM74HCT573 • MM74HCT574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC207www.fairchildsemi.com
元器件交易网www.cecb2b.com
MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-FlopPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:
2.A critical component in any component of a life support1.Life support devices or systems are devices or systems
device or system whose failure to perform can be rea-which, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life supportbody, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to thewww.fairchildsemi.comuser.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
因篇幅问题不能全部显示，请点此查看更多更全内容