Table 5-2:
CORE XCI Top-Level Port List (Cont’d)Name
stat_tx_total_good_bytesstat_tx_total_good_packetsstat_tx_bad_fcs
stat_tx_packet_64_bytesstat_tx_packet_65_127_bytesstat_tx_packet_128_255_bytesstat_tx_packet_256_511_bytesstat_tx_packet_512_1023_bytesstat_tx_packet_1024_1518_bytesstat_tx_packet_1519_1522_bytesstat_tx_packet_1523_1548_bytesstat_tx_packet_1549_2047_bytesstat_tx_packet_2048_4095_bytesstat_tx_packet_4096_8191_bytesstat_tx_packet_8192_9215_bytesstat_tx_packet_smallstat_tx_packet_largestat_tx_unicaststat_tx_multicaststat_tx_broadcaststat_tx_vlanstat_tx_pause
Size
14111111111111111111111
I/O
OOOOOOOOOOOOOOOOOOOOOO
Description
Increment for the total number of good bytes
transmitted. This value is only non-zero when a packet is transmitted completely and contains no errors.Increment for the total number of good packets transmitted.
Increment for packets greater than 64 bytes that have FCS errors.
Increment for good and bad packets transmitted that contain 64 bytes.
Increment for good and bad packets transmitted that contain 65 to 127 bytes.
Increment for good and bad packets transmitted that contain 128 to 255 bytes.
Increment for good and bad packets transmitted that contain 256 to 511 bytes.
Increment for good and bad packets transmitted that contain 512 to 1,023 bytes.
Increment for good and bad packets transmitted that contain 1,024 to 1,518 bytes.
Increment for good and bad packets transmitted that contain 1,519 to 1,522 bytes.
Increment for good and bad packets transmitted that contain 1,523 to 1,548 bytes.
Increment for good and bad packets transmitted that contain 1,549 to 2,047 bytes.
Increment for good and bad packets transmitted that contain 2,048 to 4,095 bytes.
Increment for good and bad packets transmitted that contain 4,096 to 8,191 bytes.
Increment for good and bad packets transmitted that contain 8,192 to 9,215 bytes.
Increment for all packets that are less than 64 bytes long. Packet transfers of less than 64 bytes are not permitted.Increment for all packets that are more than 9,215 bytes long.
Increment for good unicast packets.Increment for good multicast packets.Increment for good broadcast packets.
Increment for good 802.1Q tagged VLAN packets.Increment for 802.3x Ethernet MAC Pause packet with good FCS.
Integrated 100G Ethernet Subsystem v2.6PG165 February 4, 2021
Chapter 5:Example Design
Table 5-2:
CORE XCI Top-Level Port List (Cont’d)Name
ctl_rx_check_mcast_pppctl_rx_check_ucast_pppctl_rx_check_sa_pppctl_rx_check_etype_pppctl_rx_check_opcode_pppstat_rx_pause_req
Size
111119
I/O
IIIIIO
Description
A value of 1 enables priority pause multicast destination address processing.
A value of 1 enables priority pause unicast destination address processing.
A value of 1 enables priority pause source address processing.
A value of 1 enables priority pause Ethertype processing.A value of 1 enables priority pause opcode processing.Pause request signal. When the RX receives a valid pause frame, it sets the corresponding bit of this bus to a 1 and holds at 1 until the pause packet has been processed.Pause acknowledge signal. This bus is used to
acknowledge the receipt of the pause frame from the user logic.
This bus indicates that a pause packet was received and the associated quanta on the
stat_rx_pause_quanta[8:0][15:0] bus is valid and must be used for pause processing. If an 802.3x Ethernet MAC Pause packet is received, bit[8] is set to 1.
This bus indicates the quanta received for priority 0 in priority based pause operation. If an 802.3x Ethernet MAC Pause packet is received, the quanta is placed in stat_rx_pause_quanta8[15:0].
This bus indicates the quanta received for priority 1 in a priority based pause operation.
This bus indicates the quanta received for priority 2 in a priority based pause operation.
This bus indicates the quanta received for priority 3 in a priority based pause operation.
This bus indicates the quanta received for priority 4 in a priority based pause operation.
This bus indicates the quanta received for priority 5 in a priority based pause operation.
This bus indicates the quanta received for priority 6 in a priority based pause operation.
This bus indicates the quanta received for priority 7 in a priority based pause operation.
This bus indicates the quanta received for priority 8 in a priority based pause operation.
ctl_rx_pause_ack9I
stat_rx_pause_valid9O
stat_rx_pause_quanta016O
stat_rx_pause_quanta1stat_rx_pause_quanta2stat_rx_pause_quanta3stat_rx_pause_quanta4stat_rx_pause_quanta5stat_rx_pause_quanta6stat_rx_pause_quanta7stat_rx_pause_quanta8
1616161616161616
OOOOOOOO
Integrated 100G Ethernet Subsystem v2.6PG165 February 4, 2021
Chapter 5:Example Design
Table 5-2:
CORE XCI Top-Level Port List (Cont’d)Name
ctl_tx_pause_refresh_timer8
Size
16
I/O
I
Description
This bus sets the retransmission time of pause packets for global pause operation.
Re-transmit pending pause packets. When this input is sampled as 1, all pending pause packets are
retransmitted as soon as possible (that is, after the
current packet in flight is completed) and the retransmit counters are reset. This input should be pulsed to 1 for one cycle at a time.
If a bit of this bus is set to 1, the dedicated 100G Ethernet subsystem has transmitted a pause packet. If bit[8] is set to 1, a global pause packet is transmitted. All other bits cause a priority pause packet to be transmitted.System timer input for the TX. In normal clock mode, the time format is according to the IEEE 1588 format, with 48 bits for seconds and 32 bits for nanoseconds. In
transparent clock mode, bit 63 is the sign bit, bits 62:16 carry nanoseconds, and bits 15:0 carry fractional nanoseconds. Refer to the IEEE 1588v2 for the
representational definitions. This input must be in the TX clock domain.
This bit indicates that a valid timestamp is being presented on the TX.
This bus identifies which of the 20 PCS lanes that the SOP was detected on for the corresponding timestamp.Tag output corresponding to tx_ptp_tag_field_in[15:0].Time stamp for the transmitted packet SOP
corresponding to the time at which it passed the capture plane. The representation of the bits contained in this bus is the same as the timer input.
2’b00 – “No operation”: no timestamp will be taken and the frame will not be modified.
2’b01 – “1-step”: a timestamp should be taken and inserted into the frame.
ctl_tx_resend_pause1I
stat_tx_pause_valid9O
ctl_tx_systemtimerin80I
tx_ptp_tstamp_valid_outtx_ptp_pcslane_outtx_ptp_tstamp_tag_outtx_ptp_tstamp_out
151680
OOOO
tx_ptp_1588op_in2I
2’b10 – “2-step”: a timestamp should be taken and returned to the client using the additional ports of 2-step operation. The frame itself will not be modified.2’b11 – Reserved.
Note:The CMAC core samples this signal at SOP.
Integrated 100G Ethernet Subsystem v2.6PG165 February 4, 2021
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