专利名称：EPROM/flash EEPROM cell and array
configuration
发明人：Wung K. Lee,Stephen S. Chiao申请号：US07/139885申请日：19871228公开号：US04888734A公开日：19891219
摘要：An EPROM structure incorporating Vss isolation transistors having gates onwordlines shared by respective rows of conventional self- aligned EPROM cells, andhaving source and drain regions connected in series between EPROM cell source regionsand the ground Vss terminal. An isolation transistor becomes conductive only when anEPROM cell sharing its wordline is selected. During programming, otherwise possibleleakage current through unselected cells sharing the selected bitline is blocked by theVss isolation transistor. Only one unselected adjacent cell, which shares a common sourceregion with the selected cell, can leak. This leakage, if properly suppressed andcompensated, has no disturbance on unselected or selected cells during array
programming. The EPROM cell drain punchthrough voltage and channel length can thusbe reduced to obtain an EPROM cell with a low threshold voltage, low drain
programming voltage, short programming time, low cell junction and bitline capacitance,and high read current. EPROM-type products can be constructed with single low powersupplies, on-chip high voltage pumping and high speed read and programming.
Additional rows of shared isolation transistors can be formed by adding extra poly2 linesin parallel to the wordlines between EPROM source diffusions to achieve fuller
programming isolation. This cell and array isolation configuration can be extended toflash EEPROM type products.
申请人：ELITE SEMICONDUCTOR & SYSTEMS INT'L., INC.
代理机构：Rosenblum, Parish & Bacigalupi
更多信息请下载全文后查看
因篇幅问题不能全部显示，请点此查看更多更全内容