METHOD AND STRUCTURE FOR SUPPRESSING CHARGE LOSS I

专利名称：METHOD AND STRUCTURE FOR

SUPPRESSING CHARGE LOSS IN

EEPROMs/EPROMs AND INSTABILITIES INSRAM LOAD RESISTORS

发明人：JAIN, Vivek,PRAMANIK, Dipankar,NARIANI,

Subhash

申请号：EP93909193.0申请日：19930329公开号：EP0634053A1公开日：19950118

摘要：Suppression of charge loss and hot carrier degradation in EEPROMs andEPROMs, and of instability in the polysilicon pull-up resistors associated with SRAMs isachieved by the inclusion of at least one layer of silicon-enriched oxide in the MOSstructure. In such MOS structures, the silicon-enriched oxide layer may be disposedimmediately beneath the interlayer dielectric layer, or immediately beneath the inter-metal oxide layer, or immediately beneath the passivation layer, or in any combination ofthese locations. Each silicon-enriched oxide layer preferably contains at least about10.sup.17 per cm.sup.3 dangling bonds.

申请人：VLSI TECHNOLOGY, INC.

地址：1109 McKay Drive San Jose California 95131 US

国籍：US

代理机构：Cross, Rupert Edward Blount, et al

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