Fault simulation method and fault simulator for se

专利名称：Fault simulation method and fault simulator

for semiconductor integrated circuit

发明人：Masahiro Ishida,Takahiro Yamaguchi申请号：US09880976申请日：20010613公开号：US06461882B2公开日：20021008

专利附图：

摘要：A transient power supply current testing technique which affords a high level ofobservability is used to prepare a list of detectable faults including a gate delay fault, anopen fault and a path delay fault. A test pattern sequence formed by two or more test

patterns is obtained (), a train of transition signal values which occur on various signallines within the circuit when the pattern sequence is applied to operate IC under test isdetermined by a transition simulation (), and the train of transition signal values occurringon various signal lines is used to prepare a fault list which are detectable by the transientpower supply current testing when the pattern sequence is used to operate the IC undertest ().

申请人：ADVANTEST CORPORATION

代理机构：Gallagher & Lathrop

代理人：David N. Lathrop, Esq.

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